Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
As the performance and complexity of electronic systems increase, the requirement for additional memory in a system also increases. However, in order to continue to reduce the costs of the system, the parts count must be kept to a minimum. This can be accomplished by increasing the memory density of an integrated circuit by using such technologies as multilevel cells (MLC). For example, MLC NAND flash memory is a very cost effective non-volatile memory.
Multilevel cells take advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific threshold voltage (Vt) range stored on the cell. This technology permits the storage of two or more bits per cell, depending on the quantity of voltage ranges assigned to the cell and the stability of the assigned voltage ranges during the lifetime operation of the memory cell.
For example, a cell may be assigned four different voltage ranges of 200 mV for each range. Typically, a dead space or margin of 0.2V to 0.4V is between each range to keep the Vt distributions from overlapping. If the voltage stored on the cell is within the first range, the cell is storing a logical 11 state and is typically considered the erased state of the cell. If the voltage is within the second range, the cell is storing a logical 01 state. This continues for as many ranges that are used for the cell provided these voltage ranges remain stable during the lifetime operation of the memory cell.
Since two or more states are stored in each MLC, the width of each of the voltage ranges for each state is very important. The cell Vt distribution width is related to many variables in the operation of a memory circuit. For example, a cell could be verified at one temperature and read at a different temperature. The circuitry that determines if the cell is erased or programmed to the correct Vt window has to make that determination. That circuitry has some of its characteristics influenced by temperature. A Vt window is a sum of all of these types of differences, translating into a shift in the perceived window of the Vt. In order for the window to operate, the width of the four states plus a margin between each state should amount to the available window.
The available window is limited by the fact that a Vpass voltage should turn on all of the cells in the NAND series string regardless of their logic states. This is because NAND cells are read in series in a string. Once a particular cell is accessed, all other cells in that string need to act like pass gates. If the Vt of the highest cells is too high to open up the window of the Vt's then the Vpass has to be higher to allow those cells to be conductive. The higher the Vpass voltage, the more disturb condition it introduces on the cells. This is counter productive to the tight window of the cell Vt's.
One factor that causes a variation in the states that are not logical 11 is the variation due to the program verify operation. In NAND MLC, the cells are programmed upward from the source side of the string. Thus, the entire string above the programmed word line starts as erased. As discussed previously, these cells are biased with Vpass on the word line in order to turn them on when a cell is being read or verified. However, the cell conductance is impacted, depending on the cell Vt value.
For example, when cell 0 in the string experiences a verify operation, all of the 31 cells above it are in the logical 11 erased state. In other words, a Vt of −1V for each cell. If it is assumed that the data pattern for that string happens to be all logical 00, during the read operation, all of the 31 cells will be programmed with a Vt of 3V to 4V. The overdrive from the Vpass is much smaller, causing a higher drain resistance for the cell during a read operation. This causes the cell current to be degraded, translating into a potential 200 mV window loss. Since some of the cells could have remained erased or programmed with different data patterns, the amount of degradation cannot be predicted.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device that reduces the cell degradation during a program verify operation.